Non-volatile semiconductor memory cells employing floating gates which are completely surrounded by an insulative layer such as silicon dioxide are well-known in the prior art. Typically, a polycrystalline silicon (polysilicon) layer is used to form the floating gates. Charge is transferred to the floating gates through a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc.
The charge on the floating gate affects the surface channel conductivity in the cell. If the conductivity is above a certain level, the cell is deemed to be programmed in one binary state, and if the conductivity is below another level it is deemed to be programmed in the opposite binary state. These cells take a variety of forms in the prior art, some being both electrically erasable and electrically programmable, and others requiring, for example, ultraviolet light for erasing. The cells are incorporated into memories referred to in the prior art as EPROMs, EEPROMs, flash EPROMs and flash EEPROMs. (The term "flash" refers to those memory arrays in which all of the cells may be erased in a single operation).
In general, an EPROM or an EEPROM comprises a silicon substrate including source and drain regions which define a channel therebetween. Disposed above the channel is a polysilicon floating gate. The floating gate is separated from the substrate by a relatively thin gate insulative layer. A control gate is disposed above, and insulated from, the floating gate. The control gate is also commonly fabricated of polysilicon.
In the case of a flash EEPROM cell, electrons (i.e., charge) are stored on the floating gate in a capacitive manner. An example of a flash EEPROM or flash EPROM device is disclosed in co-pending application Ser. No. 07/253,775, filed Oct. 5, 1988, entitled, "Low Voltage EEPROM Cell" which application is assigned to the assignee of the present invention. The devices described in this co-pending application use asymmetrical source/drain regions and rely on the mechanism of Fowler-Nordheim tunnelling of electrons between the source and floating gate during erasing operations.
Recently, much attention has been focused on contactless, electrically programmable and electrically erasable memory cell arrays of the flash EEPROM variety. In the contactless array, cells employ elongated source/drain regions disposed beneath self-aligned thick oxide (SATO) regions. In certain instances, the drain regions are shallow compared to the source regions, while the source regions have more graded junctions. The floating gates are formed over a tunnel oxide disposed between the source and drain regions. Word lines are generally disposed perpendicular to the source and drain regions.
These arrays are sometimes referred to as having "buried bit lines" or using "contactless cells" and requiring virtual ground circuitry for sensing and programming. An example of this type of array and a process for fabricating the same is disclosed in U.S. Pat. No. 4,780,424, which application is assigned to the assignee of the present invention and which is herein incorporated by reference.
One major problem associated with the contactless array of the above-mentioned patent is diminished erase performance. The cause of the slow electrical erase performance is believed to result from an excessively thick tunnel oxide in the region near the source edge. As will be described in more detail, this thickening is inherent in the processing steps of the prior fabrication method.
Erase performance may also be degraded by defect-causing contaminants which react with the gate insulative layer. Often the gate insulative is left exposed during subsequent processing steps (e.g., etching, implantation, nitridation, etc.) This exposure frequently leads to submicroscopic defects in the tunnel oxide which greatly weaken the insulator's breakdown characteristics and electrical reliability. In other instances, the tunnel oxide is grown on a portion of the silicon substrate which has undergone significant amounts of processing, thereby affecting the quality of the oxide layer.
As will be seen, the present invention provides an improved method by which the gate insulative layer is carefully protected to control variations in thickness thereby providing improved erase performance. The invented method also results in a substantially lowered defect density in the gate oxide.
Other prior art known to Applicant includes U.S. Pat. No. 4,698,787 of Mukherjee et al., which discloses an electrically erasable programmable memory device which is programmed by hot electron injection onto a floating gate and is erased by Fowler-Nordheim tunnelling to the source region.